As is well known, the evolution of the electrical features of the processors for PCs, workstations, and servers obliges manufacturers to come up with new solutions to meet the requirements demanded by the central processing units (or “CPUs”).
In particular, a CPU of the new generation requires a high precision in the supply voltage, equal for example to +/−0.8% under steady state and +/−3% under transient conditions.
Beside these precision requirements, the supply voltages that are used decrease to 1.1V and the load currents increase up to 130 A with edges of 100 A/μs, with a requirement for efficiency higher than 80%.
Suitable current or voltage controller devices that are able to ensure the required efficiency must be used. A controller device suitable for CPU applications comprises, for example, a converter of the DC-DC interleaving type, used as an economic and efficient solution to meet the above needs and obtained by connecting in parallel N DC-DC converters in Buck or Step-down configuration (i.e., by connecting their input and output terminals to each other driven in and out of phase or interleaved mode).
Such a converter of the DC-DC interleaving type is shown in FIG. 1A. The converter 1 essentially comprises a controller 2 coupled to n buffers or phases 3 (multiphase configuration), which comprise pairs of switches, High Side and Low Side, driven by the controller 2 so as to supply a required power to a CPU 4, which is coupled to the output terminal OUT of the converter 1.
The interleaving driving of the converter 1 also implies that the controller 2 closes the High Side switches of the n phases with a phase shift equal to the switch period T divided by the number of n phases.
A multiphase interleaving converter is shown in greater detail in FIG. 1B. As shown, the converter 1 comprises n phases (indicated in the figure simply by their inductors L), with each phase 3 comprising a High Side switch SWhs coupled in series with a Low Side switch SWIs between first and second voltage references, in particular an input voltage Vin and ground GND.
Each phase 3 also comprises an inductor L coupled between a switch node X, or phase node, that is intermediate between the switches SWhs and SWIs and the ground GND. The converter 1 also comprises an output capacitor Cout connected between the output terminal OUT and the ground GND. Across the capacitor Cout there is an output voltage value Vout which is applied to the CPU 4.
The controller 2 supplies a driving signal of the PWM type for the High Side switches SWhs and the Low Side switches SWIs of the phases 3, which are sensitive to the level of the signal PWM. In particular the High Side switches are on and the Low Side switches are off if PWM=1, and vice versa the High Side switches are off and the Low Side switches are on if PWM=0. For this purpose, the controller 2 comprises a suitable modulator 5.
In recent years a great increase in the current rate has been requested by the processors (Istep/Irise), which greatly complicates the design of these DC-DC interleaving converters.
It is thus probable that the DC-DC interleaving converters of the next generation will be required to meet more and quicker load changes (“Load Transient”).
All this implies an increase in the costs of these converters for which it is necessary to increase the number of output capacitors Cout, and thus the number n of phases of the converter itself to meet the voltage tolerances requested.
In particular, if up to now the number n of phases has been selected according to efficiency, temperature of the components (i.e., reliability), and power density requirements, in the following years the number of phases will be established also according to the required current speed specifications that need to be achieved.
Increasing the number of phases is in fact a way to increase the response speed of the converter.
Clearly, for current changes equal to 70 A in a range of 50 ns, only an adequate number of ceramic capacitors can limit the voltage fall of the processor in the first 50 ns of the load transient. The regulator has a band, which is proportional to n×Fsw, with n being the number of phases of the converter and Fsw being the switching frequency, in general about 300 kHz. Thus, there are obtained response times that are in inversely proportional to the band (for example, for n=4 a response time of about 800 ns is obtained).
The converter and its response speed can thus heavily influence its manufacturing cost and the number of electrolytic capacitors to be used (which are in turn correlated to the output voltage fall for the processor over longer times with respect to the ceramic capacitors).
Band and response speed of the converter are, however, two indexes which no longer function for short load transients such as 50 ns, which can not be considered a “small signal” shifting any more since the reaction times of the closed loop system (i.e., the band) are greater by at least one order of magnitude.
Known solutions aim at improving the response times of the controller without influencing its band. An example of this type of known solution is shown in FIG. 2.
The controller 20 has a terminal OUT, for its connection with a CPU, that supplies a voltage signal Vout. The terminal OUT is coupled to a first inner terminal FB by a resistor Rfb. The controller 20 also comprises an error amplifier EA having a first inverting input terminal coupled to the first inner terminal FB and to a first current generator Gdroop suitable for supplying this first input terminal of the error amplifier EA with a voltage value Idroop equal to K*ITOT, with K being a suitable scale factor and ITOT being a total value of the current flowing in the inductors of the phases of the converter to which the controller 20 is coupled.
The error amplifier EA has a second non-inverting input terminal that receives a reference voltage Ref, and an output terminal coupled to a second inner terminal COMP of the controller 20, which is, in turn, feedback coupled to the first inner terminal FB by the series of a resistor Rf and a capacitor Cf.
The second inner terminal COMP is coupled to multiple control modules 21 that are connected in parallel and each have an output terminal O coupled to a phase of the converter.
In particular, each control module 21 is coupled between first and second voltage references, in particular a supply voltage Vdd and ground GND, and is coupled to the second inner terminal COMP.
A generic control module 21 comprises a resistor Rs and a capacitor Cs, which are connected in parallel between the second inner terminal COMP and an inner node Y of the module itself, which is, in turn, coupled to ground GND by a biasing generator Gp, which supplies a current value equal to K*IL, where K is the scale factor and IL is a value of the current which flows in the inductor L of the phase that is coupled to the control module 21.
In parallel to the capacitor Cs, the control module 21 comprises an input generator Gi, coupled between the supply voltage reference Vdd and the inner node Y, and suitable for supplying a current value equal to K*IAVG, where K is the scale factor and IAVG a value of the currents which flow in the inductors L of the phases of the converter.
The inner node Y is also coupled to a first non-inverting input terminal of an operational amplifier OA of the control module 21, which also has a second inverting input terminal that receives a ramp signal RAMP (having frequency Fsw) and an output terminal O, which is coupled to a corresponding phase of the converter and supplies this phase with a driving signal PWM.
To improve the response times of the controller 20 without modifying its band, a supplementary capacitor Cd is coupled between the first inner terminal FB and the terminal OUT, in parallel to the resistor Rfb.
In this way, when there is a particularly quick Load Transient, this supplementary capacitor Cd becomes a much smaller impedance than the resistor Rfb, resulting in the voltage value at the first inner terminal FB being no longer latched at a value equal to the reference voltage Ref (virtual ground due to the gain of the error amplifier EA) but is dragged by the voltage signal Vout present on the terminal OUT of the controller 20. The output terminal of the error amplifier EA, corresponding to the second inner terminal COMP, thus suddenly increases upwards with a speed proportional to the parameter GBWP (Gain Bandwidth Product) of the error amplifier EA and it saturates beyond the height of the PWM driving signals produced by the control modules 21.
In FIG. 2, the index j indicates the different phases of the converter coupled to the controller 20, which phases, as has been described, comprise a High Side switch SWhs coupled between an input voltage Vin and a switch node X, also called phase node, and a Low Side switch SWIs coupled between the phase node X and the ground GND, as well as an inductor L coupled between the phase node X and the terminal OUT of the converter 1 on which an output voltage value Vout is present, as well as a capacitor Cout coupled between the terminal OUT and the ground GND.
The PWM driving signals set the turn-on and turn-off times of the switches SWhs and SWIs. In particular, when the driving signal PWM is at a high value, or “1”, then the High Side switch SWhs is closed and the Low Side switch SWIs is open. In a dual way, if the driving signal PWM is at a low value, or “0”, then the High Side switch SWhs is open and the Low Side switch SWIs is closed.
Due to the configuration of the controller 20 shown in FIG. 2, the current IL which flows in each inductor L of each phase of the converter is read by the controller 20 through the scale factor K.
Although advantageous under several aspects, this known solution has two important problems.
1) Even if the controller 20 realizes a sudden and quick movement of the inner terminal COMP (further to a Load Transient), each phase responds in reality only marginally to this Load Transient and does not completely contribute to sustain the voltage value Vout required at the output due to the presence of the interleaving phase shifts of the phases themselves.
2) The speed with which the inner terminal COMP moves (a function of the parameter GBWP of the error amplifier EA) impacts how quickly the phases driven by the controller 20 are turned on or are turned on again further to a Load Transient.
It is immediately observed that the first problem is linked to the choice of the time constant of the controller 20, which is equal to Cd*Rfp, where the value of the resistor Rfb is chosen so as to program a desired droop effect (i.e., a departure of the voltage signal Vout from a reference value given by K*ITOT*Rfb, with K being generally chosen so as to determine a maximum possible value of supplied current), and the value of the supplementary capacitor Cd is chosen as high as possible so as to reduce the impedance of the parallel connection between itself and the resistor Rfb in case of a Load Transient.
However, if the value of the supplementary capacitor Cd is too high, its derivative action also occurs in the steady state (i.e., in the absence of a Load Transient, by substantially amplifying the ripple of the voltage Vout, which is a signal with a value equal to about 10 mV and recurring at frequency n*Fsw, with n being the number of phases of the converter). If this occurs, the converter becomes unsteady.
In other words, for a correct operation of the controller 20 the following relation is to be respected.½πRfb*Cd>n*Fsw where Rd is the resistance value of the resistor Rd, Cd is the capacitance value of the capacitor Cd, and n*Fsw is the frequency of the signal Vout.
All this limits the movement of the inner terminal COMP for which each phase with driving signal PWM higher than a control voltage at the instant when there is a Load Transient is only marginally turned on, as shown in FIG. 3.
In particular, in this figure it is shown how the current of the inductor of the phase F4 is only marginally interested by the Load Transient, so only three phases out of four contribute to the rise of the output voltage value Vout. This situation is valid in a general way: only n−1 phases respond to a current change associated with a Load Transient, with at least one phase remaining “lazy”.
The second problem is instead associated with the repeatability of the parameter GBWP of the error amplifier EA of the controller 20. It is known that this parameter GBWP depends on a great number of technological parameters such as oxide thickness, lithographic tolerances, diffusivity of dopants, etc. Apart from the variance with the junction temperature, a departure of at least +/−50% from a nominal value of the parameter GBWP of an amplifier is a realistic situation.
Thus, considering an error amplifier EA with nominal value of the parameter GBWP of 30 MHz (which corresponds to a value of A0 equal to 100 dB and to a pole at 300 Hz), in practice the value of the parameter GBWP could vary between 15 MHz and 45 MHz.
By repeating the simulations on the known controller 20 with error amplifiers EA having the two extreme values indicated above for the parameter GBWP, the patterns shown in FIGS. 4A and 4B are obtained, which highlight the dependency of the change of the output voltage Vout on the real value of the parameter GBWP of the error amplifier EA.
It is thus occurs that, if for GBWP=45 MHz three phases out of four respond to the Load Transient, for GBWP=15 MHz only two phases out of four respond to the same Load Transient. Thus, the fall value of the output voltage Vout of the converter passes from 110 mV (with GBWP of 45 MHz) to 125 mV (with GBWP of 15 MHz).
Moreover, the known solution does not have any control during the la release step of the load and is not able to “follow” sudden decreases of the current requests under these release conditions with the production of undesired over-elongations of the output voltage value.
To try to solve this problem a “body-brake” technique has recently been proposed, as described for example in U.S. Pat. No. 6,806,689. A method for controlling a converter of the multiphase interleaving type which uses the body-brake technique provides that, under release conditions of the load, all the High Side and Low Side switches are off (while traditionally, that is in case of controllers which do not use this body-brake technique, the controller turns off the High Side switches but turns on the Low Side SWIs switches).
In this way, the over-elongation (or overshoot) of the output voltage Vout further to the release of the load is widely decreased with respect to controllers which do not use this body-brake technique. In fact, the excess of charge dQ generated by the zeroing of the currents of the inductors L of the phases of the multiphase interleaving converter is decreased due to the presence of Low Side switches off.
In particular, in the case of traditional controllers, this excess of charge is equal to the following.dQ=L/Vout*Ipeakwith |peak being a value of a residual current in the inductors L of the phases of the converter, the voltage fall to the ends of these inductors L being equal to the output voltage Vout.
To the contrary, by using the body-brake technique, the voltage fall to the ends of the inductors L is equal to Vout+Vdiode, with Vdiode being the voltage value to the ends of the intrinsic diode of the Low Side switches under shut off conditions.
Thus, the fall to the ends of the inductors L is decreased due to the voltage fall on these intrinsic diodes and the excess of charge is given by the following.dQ=U(Vout+Vdiode)*Ipeak.
Due to this decrease of the charge excess dQ, a decrease of the overshoot of the output voltage Vout is obtained.
The turn-on and turn-off conditions of the Low Side switches are shown in FIGS. 5A and 5B, and the corresponding patterns of the current values in the inductors of the phases and of the output voltage are shown qualitatively in FIGS. 5C and 5D.
In particular, it is known to detect the release conditions of the load by comparing a control voltage Vcntr (corresponding to an output voltage of the error amplifier EA, that is the voltage value COMP) with a reference voltage Vr as well as with a coupling voltage Vclamp of the body-brake.
Normally, the reference voltage Vr has a ramp-like or saw-tooth periodic waveform, as shown in FIG. 5E. The turn-on (ON) and the turn-off (OFF) of the High Side and Low Side switches is then decided according to the following rules.
if Vctr>Vr, then High Side ON and Low Side OFF;
if Vctr<Vr and Vcntr>Vclamp, then High Side OFF and Low Side ON; and
if Vctr<Vr and Vcntr<Vclamp, then High Side OFF and Low Side OFF, with this latter condition corresponding to the body-brake technique.